DIGITAL INTEGRATED CIRCUIT DESIGN
Academic year and teacher
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- Versione italiana
- Academic year
- 2017/2018
- Teacher
- DAVIDE BERTOZZI
- Credits
- 6
- Didactic period
- Secondo Semestre
- SSD
- ING-INF/01
Training objectives
- The course objective is to provide the basic notions on the design methodologies (both front-end and back-end) for
the architectures of digital integrated systems (or systems-on-chip).
The knowledge that will be provided can be listed as follows:
- Understanding of the steps of a front-end synthesis flow for digital integrated systems,
based on the principle of the successive refinements of abstraction layers.
- Understanding of the steps of a back-end synthesis flow starting from a technology-independent
specification and ending up in a concrete implementation on top of a technological substrate.
- Understanding of the protocols and of the topologies that characterize an on-chip communication architecture,
acting as the system integration framework.
- Understanding of the key design concerns for parallel computing architectures: memory consistency and memory coherence.
The basic skills that will be developed concern:
- The modeling of an architectural block at the RTL abstraction layer by means of the SystemC hardware description language.
- The modeling and simulation of both hardware and software blocks in a unified modeling and simulation environment.
- The transformation of an RTL specification into a technology-dependent implementation.
- The assessment of solutions that modern multi-core processors for embedded systems adopt to tackle the memory
consistency and coherence challenges.
- The interconnection of functional blocks of an integrated system through the right protocol-topology combination
that meets the communication requirements of the system at hand. Prerequisites
Course programme
- - International Technology Roadmap for Semiconductors: the system drivers
- SystemC modeling and simulation framework: basics
- Interface Method Calls
- SystemC scheduler and dynamic sensitivity
- Primitive and hierarchical channels
- SystemC modeling case studies at different abstraction layers
- Design methodologies for digital integrated systems: overview
- Full-custom design methodologies
- Cell-based design methodologies
- Array-based design methodologies
- Soft and Hard Macrocells
- Systems-on-Chip
- The interconnect delay bottleneck: a cross-layer concern
- The System-on-Chip global integration framework: an overview
- Communication protocol features for on-chip communication
- Topological solutions for on-chip communication
- Review of industrial on-chip communication solutions:
- AMBA APB and AHB
- MULTI-LAYER AHB
- AMBA AXI
- Basic networking principles
- Design techniques for on-chip interconnection networks
- Design issues for parallel computing architectures: an overview
- Memory consistency models
- Sequential consistency and its relaxation
- Basic principles to maintain cache coherence
- Snoopy-based cache coherence protocols
- Directory-based cache coherence protocols Didactic methods
Learning assessment procedures
- The goal of the exam is to test the achievement of the following concepts:
- (skill) architectural modeling through C/C++-based hardware description languages.
- (understanding and skills) design and synthesis methodologies, both front-end and back-end.
- (understanding) system-level on-chip communication: protocols, topologies, micro-architectures.
- (understanding) design issues for parallel computing architectures.
The exam is split into two parts:
1) Delivery of a report and source code relative to an assigned project,
consisting of the modeling and simulation of an architectural block, and face-to-face
discussion of the report with the professor. This part completes the laboratory exercises
held during the course, and aims at assessing skills in modeling and simulation with SystemC. The maximum mark is 5/30. There is no minimum mark:
if the report is not satisfactory, the student is obliged to improve it until it matches standard criteria agreed with the professor.
2) Oral exam where the focus will be on the capability to critically link concepts presented
throughout the course with one another, rather than on the formally-perfect presentation of specific concepts.
The exam consists of three questions, which typically span from design methodologies to
interconnection techniques, going through computation architectures. The maximum mark is 25/30.
The two parts of the exam are independent, in the sense that the first one can be passed before
the second one, or vice versa. Reference texts
- The course takes an interdisciplinary approach to the field of system-on-chip architectures, and even presents frontier topics for industrial research. Therefore, the following textbooks are suggested in order to consolidate the understanding of specific topics that will be pointed out during the lectures, but they do not provide any complete overview of those topics:
1. Digital Integrated Circuits - A Design Perspective (second edition), J.M.Rabaey, A.Chandrakasan, B.Nikolic, Prentice Hall
2. Computer Organization and Design: The Hardware/Software Interface, Third Edition
(The Morgan Kaufmann Series in Computer Architecture and Design), David A. Patterson, John L. Hennessy (Paperback - August 2, 2004)
3. Design of High Performance Microprocessor Circuits, A.Chandrakasan, W.J.Bowhill, F.Fox, IEEE Press, 2001.
4. Principles and Practices of Interconnection Networks
(The Morgan Kaufmann Series in Computer Architecture and Design) William James Dally, Brian Patrick Towles Morgan Kaufmann, 2004
5. System Design with SystemC, T.Groetker, S.Liao, G.Martin, S.Swan Kluwer Academic Publishers 2002
6. Designing Network On-Chip Architectures in the Nanoscale Era, J.Flich & D.Bertozzi, CRC Press, 2011.
Lecture slides and lab. material are provided on the course website.
