Salta ai contenuti. | Salta alla navigazione

Strumenti personali


Academic year and teacher
If you can't find the course description that you're looking for in the above list, please see the following instructions >>
Versione italiana
Academic year
Didactic period
Primo Semestre

Training objectives

The Data Storage course examines in detail the semiconductor devices, the circuits and the architectures necessary for storing information in the most disparate scenarios of electronics, from the embedded world to data centers.

The main objective of the course is to provide students with the basics to understand the memory hierarchy in an electronic system and to deal with the analysis of the components necessary to implement data storage under the constraints of performance, reliability and power consumption dictated by the application that will interact with the data. The tools provided will therefore form the basis of the design of an optimized storage environment.

The main knowledge acquired will be:
- Theoretical elements of information storage on electronic devices.
- Technologies and characteristics of the circuits to store a few quantities of data in the order of hundreds of bits (Flip-Flop and registers).
- Technologies, circuits and architectures for the realization of volatile memories (SRAM and DRAM) with capacities from a few MBytes up to ten GBytes
- Technologies, circuits and architectures for the realization of non-volatile semiconductor memories with high storage density (NOR Flash and NAND Flash)
- Solid state disk architecture (SSD) for storing large amounts of data (up to ten TBytes per disk) and managing their reliability / performance
- Management of hyper-scaled storage solutions in environments such as data centers or High Performance Computing (HPC)
-Innovative memory technologies and architectures such as RRAM, PCM and STT-MRAM
- Innovative storage applications such as In-Memory Computing, In-Storage Processing and Computational Storage

The main skills (i.e. the ability to apply the knowledge acquired) will be:

- Identify the ideal memory technology for a given application context.
- Evaluate storage performance and reliability constraints according to the chosen technology and consequent optimization of the memory hierarchy.
- Design a storage environment based on solid state drives.


To follow the course it is necessary to have understood and studied the concepts of:

- Digital electronics relating to structures and digital circuits for the logical manipulation of data
- Microprocessor systems as regards the architecture of a processing system and Boolean algebra

In any case, references to these concepts are foreseen in the course to facilitate the understanding of some specific topics of the course. It is not necessary to have passed the associated exams to take the exam.

Course programme

The course includes 60 hours (45 hours of classroom teaching, 12.5 hours of in-depth analysis through group activities and focus groups and a 2.5-hour seminar held by a data storage engineer).

Introduction to the course (2.5 hours)
- Introduction to the world of data storage
- The current memory hierarchy in electronic systems
- Technological trends and hierarchical innovation
- CPU, GPU and FPGA: what does storage have to do with it?
- Artificial Intelligence (AI), Internet-of-Things (IoT) and Big Data seen from the perspective of storage
- Considerations on current storage limits: reliability, performance and power consumption

How to memorize a bit or so (2.5 hours)
- The bistable multivibrator circuit and the latches
- Flip-Flops (D and JK type)
- Performance (setup and hold times, propagation delay)
- Store a word (a byte or a little more ...): registers and their architecture
- Construction features and design considerations
- Pipelining of operations involving the registers

SRAM memories (2.5 hours)
- The SRAM memory cell (read and write operations)
- Layout and architecture of the bitlines
- Peripheral circuitry (decoders, sense amplifiers, conditioning of the bitlines)
- Multi-port architectures
- Using memory as an off-chip cache (performance analysis)

DRAM memories (5 hours)
- The DRAM memory cell (read and write operations)
- Memory layout and architecture
- Array structure and DRAM subsystem
- DDR, LPDDR and GDDR protocols
- Command accessing
- Signal integrity and power consumption
- Reliability (row-hammer attack and retention issues)
- High Bandwidth Memory

Introduction to non-volatile memories (2.5 hours)
- ROM (architecture and general information on their use)
- Tunnel effect (Fowler-Nordheim) and hot electrons
- The FLOTOX transistor
- Notes on EEPROM architecture
- Charge pumps

NOR Flash memories (2.5 hours)
- Architecture and layout of a NOR Flash memory chip
- Read, write and erase operations
- Peripheral circuitry for reading and writing operations
- Algorithms for checking reliability
- Gate and Drain disturb
- NOR Flash subsytem
- SPI NOR and eXecute in Place (XiP)

NAND Flash memories (7.5 hours)
- Architecture and layout of a NAND Flash memory chip
- Read and write operations (concept)
- Peripheral circuitry for reading and writing operations
- Algorithms for controlling operations and reliability
- Multi-level paradigms
- Flash memory subsystem (command interface)

3D NAND Flash architectures (2.5 ore)
- 3D stacking die concept
- BiCS and p-BiCS
- TCAT and V-NAND for terabit storage

Solid State Drives (SSDs) (7.5 hours)
- Architecture of an SSD
- Comparison between SSD and HDD
- SSD controller
- NAND memory organization
- Host Interface: SATA, SAS, PCIe
- DRAM buffers and caching techniques
- SSD modeling
- Adaptive NAND processing techniques
- Hybrid storage: SSD for enterprise applications

Storage in data centers (5 hours)
- Introduction to the HPC world
- On-premise and distributed storage platforms
- The NVMe protocol
- In-storage processing (KV-store, genomics, etc.)
- Computational storage

Emerging non-volatile storage technologies (2.5 hours)
- PCM memories
- MRAM memories
- FeRAM memories
- RRAM memories

In-memory computing (2.5 hours)
- Use RRAM memory technology as an example to create fast neural networks
- Neuromorphic tasks
- High-speed arithmetic and MAC operations with RRAM

Didactic methods

In the academic year 2021/2022, the course will be delivered in mixed or "blended" mode (simultaneously both in presence and in distance learning) in accordance with the provisions in force relating to the COVID emergency.

All lessons will be recorded and made available on Classroom from midnight the day after delivery in the classroom (code vzvttsz, access with the @ account credentials).

On a bi-weekly basis there will be either a face-to-face meeting or a live meeting (Focus Group) for question / answer sessions on the course contents. The event will be open to both students attending these sessions in person and remotely. The day and time of delivery of the Focus Group will be indicated on the classroom of the course at least one week in advance to allow students to organize themselves.

Learning assessment procedures

The objective of the exam is to verify the level of achievement of the previously indicated training objectives.

The exam consists of an oral test on all the topics of the course which aims to evaluate the student's preparation on the theory and verify the student's ability to connect the course contents for their future application. The test also aims to train the student in the oral presentation of their knowledge and skills, with a training effect in the field of Soft Skills.

The student will be assigned 3 macro-topics and the student, before exposing them, will be able to organize the answer (generally from 30 'to 60', depending on the student's needs).

Given the complexity of many circuit and architectural schemes, the student is not required to know how to redraw them from memory. The student can use the schemes seen in class and on which he studied. The objective of the study, in fact, is not to remember patterns that will probably no longer be used in a few years, but to have understood the theoretical, applicative and economic reasons that led to the definition of those specific solutions.

The student's preparation will therefore not be assessed on the ability to remember, by heart, schemes or formulas, but in the ability to explain the reasons that lead to specific circuit choices and in identifying potential limits.

Passing the exam is proof of having acquired the knowledge and skills specified in the educational objectives of the course.

The exam can also be taken in English.

Reference texts

Notes and material provided by the teacher available on the course website and on the reference Classroom.

Specific topics can be explored on the following texts:

- Bruce Jacob, Spencer Ng, and David Wang. 2007. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA.

- Weste, Harris, “CMOS VLSI Design,” 2nd Ed., Addison Wesley.

- R. Micheloni, A. Marelli, K. Eshghi; Inside Solid-State Drives (SSDs) 2nd Ed .; Springler-Verlag, 2018