EMBEDDED SYSTEM ACHITECTURES
Academic year and teacher
If you can't find the course description that you're looking for in the above list,
please see the following instructions >>
- Versione italiana
- Academic year
- 2021/2022
- Teacher
- DAVIDE BERTOZZI
- Credits
- 6
- Didactic period
- Secondo Semestre
- SSD
- ING-INF/01
Training objectives
- The main learning objective is to provide basic notions on the architectures and on the synthesis methodologies (both front-end and back-end) of systems-on-chip for the embedded computing domain.
Acquired knowledge will include:
- Knowledge of the front-end synthesis steps based on the principle of the progressive refinement of the abstraction layer. To this end, knowledge of the SystemC modeling and simulation language.
- Knowledge of the back-end synthesis steps, changing a technology-independent specification into a mapped gate-level implementation based on a generic technology library. To this end, knowledge of the semi-custom design methodology based on standard cells.
- Knowledge of the "HOST CPU" performing control tasks in modern heterogeneous parallel computing architectures. Knowledge will include CPU microarchitectures and optimization techniques for performance.
- Basic knowledge of the "Single Instruction Multiple Data" processing and of GPU architectures.
- Knowledge of the memory hierarchy and of its management techniques, both in hardware and in software.
- Basic knowledge of the different acceleration methods of computation kernels, both through hardwired accelerators and through reconfigurable logic.
- Knowledge of protocols, topologies and architectures for on-chip communication, in order to implement the global system integration framework.
The main abilities students will gain include:
- Ability to model an architectural block at the transactional or RTL level through the SystemC modeling and simulation language.
- Ability to model and simulate both the hardware and the software through a unique programming/description language.
- Ability to change a specific RTL description into a gate-level implementation, mapped onto a generic technology library.
- Ability to understand the classification of the "application processors" used in modern embedded systems, to capture their differences and to assess their performance-power trade-off.
- Ability to assess the solutions that modern multi-core processors provide to the memory consistency and coherency problems.
- Ability to understand the leading role of GPU architectures in the exploitation of parallelism in modern applications.
- Ability to understand and make use of reconfigurable logic.
- Ability to interconnect functional blocks of a system-on-chip through the best combination of communication protocols and topologies given the requirements of the system at hand. Prerequisites
- Key pre-requisites include basic notions from the courses of:
- Digital Design: CMOS logic, on-chip interconnects, transient behaviour, fabrication methodologies.
- Computer Architecture: instruction set architecture, single-core microarchitecture, pipelining, data hazards, caching, computer arithmetic, assembly programming. Course programme
- - Introduction to Embedded Computing, and its positioning in the context of global computing frameworks.
- Architectural template of a System-on-Chip (SoC).
- Front-end system-on-chip design methodologies based on SystemC.
- SystemC syntax and Lab exercises.
- Communication semantics in SystemC: Interface Method Calls.
- SystemC scheduler and dynamic sensitivity.
- Primitive and hierarchical channels.
- Recalling Instruction Set Architectures.
- Recalling pipelines, hazard detection units, forwarding units.
- Branch prediction techniques: static and dynamic ones.
- Architectures with multiple "execution paths" and reorder buffer.
- Architectures with out-of-order scheduling.
- Superscalar architectures.
- VLIW architectures.
- Single-Instruction Multiple-Data processing and GPU architectures.
- Basics of standard cell design methodologies, hard macros and soft macros.
- Basics of FPGA architectures.
- Memory hierarchy.
- Virtual memory.
- Cache coherence protocols: snooping, directory-based.
- Protocols and topologies for on-chip communication in low-end systems: AMBA AHB, AMBA AXI.
- On-chip interconnection networks: topologies, routing, flow control, switching and architectures. Didactic methods
- The course is structured in the following way:
- Lectures on all course topics, taking roughly two-third of the total number of hours. The teaching methodology revolves around the projection of slides that will be made available at least one hour before each lecture. Lectures will be very interactive, in order to develop the critical thinking skills of students as well as their ability to argue their viewpoints on technical issues.
- Guided Laboratory exercises in the (small) Informatics Lab aiming at modelling architectural blocks through C/C++-based hardware description languages. Each student will have his own working station and directory, and will follow such guided Lab activities for roughly one-third of the total amount of hours.
Beyond the guided Lab activities, students will have free access to the Informatics Lab (during available hours) so to be able to practice more. As an alternative, it is possible to install the simulation software directly on the students' laptops so to give them the maximum flexibility in planning their study schedule. Learning assessment procedures
- The goal of the exam consists of verifying the extent to which the following learning objectives have been achieved:
- (ability) Architecture modelling through C/C++-based hardware description languages.
- (knowledge) Design and synthesis methodologies of systems-on-chip, including both front-end and back-end methods.
- (knowledge) Design and optimization techniques of single-core micro-architectures, and fundamental functional issues in multi-core systems.
- (knowledge) Design and management methodologies of memory hierarchies.
- (knowledge) Basics of hardware/software acceleration frameworks of computation kernels.
- (knowledge) Interconnection techniques of architectural building blocks at the system level: protocols, topologies and architectures.
The exam is split into two parts:
- Achievement of a pass/fail evaluation of Lab exercises.
- Oral Exam.
A) Pass/Fail evaluation of Lab exercises.
Lab activities are structured as a predefined sequence of guided Lab experiences. For each of them, students have to get a "pass" evaluation that certifies the progressive and solid increments of his maturity in hardware modeling and simulation. Once a "pass" is obtained in each Lab exercise, the student is entitled to pass the exam.
B) Oral exam.
In the oral exam the student's ability to expose topics in an appropriate and rigorous way will be tested. At the same time, the oral exam intends to test his ability to establish logical links between affine topics covered during the course. The oral exam consists of three questions, that tentatively cover most of the topics addressed by the instructor during the lectures.
The two parts of the exam are not subject to temporal constraints: the pass/fail evaluation can be obtained before or after the oral exam. A "pass" in the Lab exercises entitles the student to pass the exam (i.e., to confirm the mark of the oral exam, regardless it has been already passed or not); it is not a requirement to be admitted to the oral exam. The final mark is thus the mark of the oral exam only. Reference texts
- The course takes an interdisciplinary approach to the design and optimization of systems-on-chip for the embedded computing domain, and often addresses topics that are at the frontier of scientific or industrial research. For this reason, no existing book can cover all topics addressed by the lectures. Instead, a list of books is suggested to cover different topics. Students will be referred to the specific books during the lectures depending on the topic at hand.
1. Digital Integrated Circuits - A Design Perspective (second edition), J.M.Rabaey, A.Chandrakasan, B.Nikolic, Prentice Hall
2. Computer Organization and Design: The Hardware/Software Interface, Third Edition
(The Morgan Kaufmann Series in Computer Architecture and Design), David A. Patterson, John L. Hennessy (Paperback - August 2, 2004)
3. Computer Architecture: a Quantitative Approach, J.Hennessy and D.Patterson, Morgan Kaufmann, 2017.
4. Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools.
Book by Joseph A. Fisher, Paolo Faraboschi, and Cliff Young; Morgan Kaufmann, 2005.
5. Computers as Components: Principles of Embedded Computing System Design (2nd edition). Wayne Wolf - Morgan Kaufmann, 2008.
6. Principles and Practices of Interconnection Networks
(The Morgan Kaufmann Series in Computer Architecture and Design) William James Dally, Brian Patrick Towles Morgan Kaufmann, 2004
7. Designing Network On-Chip Architectures in the Nanoscale Era, J.Flich & D.Bertozzi, CRC Press, 2011.
8. System Design with SystemC, T.Groetker, S.Liao, G.Martin, S.Swan - Kluwer Academic Publishers 2002.
Projected slides during the lectures will be made available on the course website (http://mpsoc.unife.it/~arch-dig/), together with the specifications of the Lab activities.
