Salta ai contenuti. | Salta alla navigazione

Strumenti personali


Academic year and teacher
If you can't find the course description that you're looking for in the above list, please see the following instructions >>
Versione italiana
Academic year
Ingegneria informatica - Sistemi di elaborazione
Didactic period
Primo Semestre

Training objectives

The course provides some basic concept in design automation and verification of digital systems


Basics of digital systems' design and simulation based verification at different logic levels. The role of design automation tools. Syntax and semantic of the hardware description language VHDL. Performance of digital systems. High-level synthesis and optimization of digital systems.


Capability to write VHDL models of medium sized digital blocks described at different abstraction levels (gate, RTL, architecture).

Capability to verify such models by using logic level simulation.

Capability to analyze simple high-levels algorithms and to synthesize and optimize them.


Basic knowledge of digital modules and switching theory. Basic concepts of programing languages. Elementary concepts of computer architecture.

Course programme

1) Introduction to digital systems design and verification:
1.1) description levels
1.2) logic synthesis and verification
2) The VHDL language
2.1) syntax and semantic
2.2) the VHDL role in simulation and synthesis
2.3) modeling and synthesis of digital modules
3) Digital systems performance
3.1) metric (cost, throughput and latency)
3.2) clock frequency constraints
3.3) static timng analysis
3.4) performance improvement: architectural and gate level techniques
4) High-level synthesis
4.1) Data Flow Graph and Control Flow Graph extraction from high-level algorithm descriptions
4.2) allocation and scheduling
scheduling algorithms for design optimization
5) Introduction to FPGA technologies

Didactic methods

The course consists of frontal lessons and laboratory exercises with the use of design automation tools.

Learning assessment procedures

The exam is divided in 3 parts:

1) a brief report on one laboratory activity chosen between those performed during the course (0-2 points) is required to verify the understanding of such exercises (to be presented before of the begin of the summer exam session of the course's year);
2) a written partial exam with simple exercises regarding either the course theory or the modeling and optimization of small digital modules (0-15 points);
A first kind of exercises requires the implementation of a VHDL model aimed at verifying the understanding of the VHDL timing model or the capabiliy to describe combinational or synchronous digital components. Another kind of exercises is aimed to the verification of the knowledge of methods used to analyze and improve the performance of digital systems by applying scheduling algorithms to data-flow graphs.
3) a project whose theme is assigned by the teacher (0-15 points). Each project requires the understanding of one of course topics, its and its application to a specific design or verification problem,
The exam outcome is positive if the student achieves at least 9 points in the written exam and 9 points in the project, thus proving the acquisition of the knowledges and abilities specified in the targets of this course. The written exam and the project can be performed in any order and a possible positive evalutaion does not have timing constraints.

Reference texts

Handouts provided by the teacher and available on the course website.

Suggested textbook as a refernce for VHDL language:
Zwolinski M. , VHDL - digital systems design, Pearson - Prentice-Hall