ALU test bench

Contenuto del file

-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

entity tb is 
end entity tb; 

architecture behav of tb is 
signal a,b,res: std_logic_vector(7 downto 0); 
signal op: std_logic_vector(2 downto 0); 
signal zero,sign: std_logic; 

begin 

alu0: entity work.simple_alu(behav) port map 
                (a=>a,b=>b,op=>op,r=>res,zero=>zero,sign=>sign); 
                
                p0: process
                begin
                wait for 5 ns; 
                a <= "00000001"; 
                b <= "00000110"; 
                op <= "010"; 
                wait for 5 ns; 
                op <= "001";
                end process; 
                
end behav;