The files b0*_opt_C.vhd are combinational data-flow descriptions 
of the combinational part of benchmark circuits. 

The files b0*_opt_C_mapped.vhd are combinational structural descriptions 
of the combinational part of benchmark circuits. They are mapped on a generic 
library that must include: 
nand2
nand3 
nand4
nor2
nor3 
nor4 
and2 
or2 
not 
buff 

The gate models must have the input list as the first port parameters and 
the output as the last port parameter. 

The delay of each block is computed as dintr+d*fo, 
where dintr=30 ps and dfo=20ps. The model is oversimplified.
