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NaNoC

Nanoscale Silicon-Aware Network-on-Chip Design Platform

 

Logo NanoC

 

 

 

 

 

Project details:

Call: FP7 - Information & Communication technologies

Start date 1/01/2010 - end date 31/12/2012

Total cost: 4.117.601 €

EU contribution: 2.925.000 €

EU contribution to UniFe: 412.050 €

 

Abstract:

The NaNoC project aims at developing an innovative design platform for future Network-on-Chip (NoC) based multi-core systems. This NaNoC design platform intends to master the design complexity of advanced microelectronic systems by enabling strict compon

ent oriented architectural design. A compositional approach to NoC design in future multi-core chips is out of the reach of current design methods and tools due to new design constraints. Requirements for co-design with high-level platform management frameworks facilitates a need for enhanced dynamism and flexibility in NoC composition (e.g., virtualization, power management, thermal management, application management). On the other hand, a higher degree of uncertainty originating from nanoscale integrated circuit fabrication technologies raises the need to build reliable systems out of unreliable components.The NaNoC design platform provides design methods and prototype tools to cope with both challenges and to make NoCs a mainstream interconnect backbone for effective system integration. The platform enables NoC component assembly at each layer of the design hierarchy. Therefore, design for manufacturability techniques and tools are developed to preserve yield in the presence of manufacturing defects and circuit performance/power variability.Above all, the NaNoC design platform fosters tight cooperation between system research, circuit design and process development by means of a silicon-aware decision making at each layer of the design hierarchy. In this direction, NaNoC not only provides a cross-layer approach to tackle composability challenges (e.g., physical design techniques for enhanced reliability combined with architecture-level techniques for fault containment), but also defines an exchange format for interoperability between design tools for cross-layer optimization. Interoperability between developed NoC design methods/prototype tools and mainstream design toolflows will also be pursued.

 

Participants:

  • Universidad Politécnica de Valencia, Coordinator (Spain)
  • INTEL MOBILE COMMUNICATIONS GMBH (Germany)
  • Infineon Technologies AG (Germany)
  • Simula Research Laboratory AS (Norway)
  • Teklatech A/S (Denmark)
  • iNoCs SàRL (Switzerland).